This invention relates to methods for generating test programs for identifying faults on a loaded printed wiring board and, more specifically, for automatic program generation of such test programs employing a data processor.
During the manufacture of printed wiring boards loaded with electrical components, it is common to encounter faults, such as reversal of components, missing components, components of the wrong value and erroneously placed components. Techniques have been developed which use test or fixture systems with associated electronics for testing finished loaded printed wiring boards for such defects.
Such systems can generally be classified into two groups, known as functional testers and in-circuit testers. Functional testers are devices which connect to the edge of the printed wiring board and apply test signals at the edge of the board to determine if the loaded board contains any faults. An in-circuit tester is one which tests for the integrity of individual components and utilizes what is commonly known as a bed of nails. The bed of nails includes an array of probes which contact various test points over the printed wiring board and thereby allows test signals to be applied between pairs of such test points.
Functional testers suffer from a number of disadvantages. For example, complex software is required to isolate of diagnose faults and such testers can only apply and sense signals at the edge of the printed wiring board. As a result, it is difficult to identify faults at specific components. To identify a specific fault, it is necessary to take the results of the test at the edge of the printed wiring board and use them to apply a series of manually probed measurements to that portion of the circuit producing the defective test.
Techniques have been devised for generating test programs to direct the sequence of operations to be carried out by a test system in testing printed wiring boards. A test program list is a sequence of instructions which directs the sequence of steps that the test system is to go through to test a printed wiring board. One technique employed is generally referred to as automatic test program generation. The purpose of automatic test program generation is to generate a program which will cause the printed wiring board test system to detect and report defects in the loaded printed wiring board.
The commonly used techniques for test program list generation for in-circuit testers can generally be classified into six classes, as described below.
The first class involves the N-squared technique and is largely theoretical, since it is generally impractical to fully implement. However, it is instructive to discuss the N-squared technique as a backdrop for other methods. The N-squared technique produces a test program list which lists each different pair of test nodes on the printed wiring board and the electrical measurement to be made between each such pair. If a program is generated consecutively to test from each test node to every other test node on the loaded printed wiring board, it results in an extremely large list of test nodes and measurements, the number of such measurements being almost the square of the number of test nodes times the number of measurement types. This requires an extremely large and unwieldy program and takes a substantial amount of time to generate and implement. By way of example, the number of test nodes for a loaded printed wiring board having N different test nodes would be as follows: N* (N-1)* TYPES, where N is number of test nodes and TYPES is the number of different types of tests to be performed. For example, the types of tests that may be performed include resistance measurement, capacitance measurement and junction measurement. Thus, if there are 1,000 different test nodes on the printed wiring board and three types of electrical measurements are to be conducted, the number of measurements would be: 1,000* (1,000-1)* 3=2,997,000. This assumes that all three measurement types are conducted between each pair of test nodes.
The second class is the manual method. In the manual method, technicians or programmers select pairs of test nodes (nodes are also called points) on the loaded printed wiring board corresponding to the electronic component to be tested and the type of measurement to be made between each such pair of test nodes. The problem with this approach is that it requires an inordinate amount of time to manually create such a program with all the required test node pairs, and carefully analyze the circuit to determine nominal values of components and determine minimum and maximum values, and other required data. For example, in determining the nominal value of a component which comprises two resistors in parallel between the associated test nodes, the user must determine the effective resistance between the test nodes to select the nominal value for the corresponding pair of test nodes. If there is a semiconductor junction connected between a pair of test points, the user must specify the polarity at which the junction test is to be made.
The third class involves a process whereby the circuit on the printed wiring board is analyzed and a list of each different test node on the printed wiring board is made including, for each test node, a list of the components connected to that test node and the nominal value of the component. The resultant list is then manipulated by a data processing machine to create a list of pairs of test nodes to be tested by the fixture system.
The fourth class involves what is known as the nodal impedance method. In this technique, tests are applied from each test node to all the other test nodes with all other test nodes shorted together. A measurement is made of the "characteristic impedance" between the test nodes. A serious shortcoming of this technique is that when one shorts a number of nodes in the circuit together, one could be connecting, for example, resistors having very large values of resistance in parallel with resistors having very low values of resistance so that the resultant test between the test nodes may be virtually meaningless when the small resistance masks the presence of the large resistance. Additionally, when one connects large groups of resistors, capacitors and other components in parallel, it is virtually impossible to relate the resultant test to any particular component. For example, it would be very difficult to determine whether nominal values of resistors are within a desired tolerance or to determine if a resistor of a very high value is missing if it is in parallel with a resistor of a very low value. A resistor with an allowable nominal value tolerance of ten percent in parallel with a resistor only ten times larger will cause the resultant nominal value to vary only ten percent if the larger resistor is missing. With this technique, one cannot measure specific values for specific components, cannot select tolerances of specific measurements, and cannot test for junctions. One system in this class of system is an automatic program generator. When generating a test program list with nominal values, the programmer must select a sampling of typical boards, measure the characteristic impedance between each test node and all other points shorted together and average the resultant characteristic impedances between each test node and all other nodes shorted together among all the boards to come up with a characteristic impedance to be used in the test program list.
In the fifth class designed in part for testing logic boards for misplaced or missing pull-up resistors, the circuit is analyzed to identify the +5 volts and ground conductors. These nodes and other test nodes on the printed wiring board are then used in conjunction with a continuity and isolation test method described in the Long U.S. Pat. No. 4,114,093 to produce a preliminary test program list of test pairs. A test signal is then applied across the test nodes in each pair. Specifically, a current is applied between test nodes to see if voltage rises continuously or levels off at some point. If the voltage does not level off within a selected time interval, it is assumed that the component connected between the test nodes is not a pull-up resistor and the particular pair of test nodes is deleted from the test program list. If it stabilizes, it is assumed that a pull-up resistor is connected between the test nodes. A measurement is made by counting the number of regularly occurring time ticks or clock signals that occur during the rise in voltage. This technique is designed principally to test printed wiring boards for computer circuits with TTL-type logic. Typically, the faults in this type of circuit are opens, shorts and missing pull-up resistors. This technique has certain disadvantages which make it difficult to apply to general digital logic circuits and non-digital logic circuits.
The sixth class requires the user to select and manually input pairs of test nodes and specify whether a capacitance, resistance or junction measurement type is to be made between each such pair of test nodes. The system then automatically applies the specified measurement type between each of the specified pairs of test nodes and, in effect, self-learns the actual electrical component nominal values on a loaded printed wiring board. However, this technique does not involve any means for displaying the resultant measurement, nor does it have any provision for allowing the user to edit the results of the measurements.
Because of the deficiencies in the prior art, there is a need for a better and more efficient method for automatic test program list generation where the test program list is for detecting and reporting defects in printed wiring boards, materials and workmanship.